1. Field of Invention
The present invention relates to a digital-to-analog converter (DAC), and more particularly to a DAC which phase by phase outputs the digital signal according to N timing signals.
2. Description of the Related Art
In terms of the mechanism for driving a display panel of a conventional thin film transistor liquid crystal display (TFT LCD), a source driver is used to provide the analog signal required for driving pixels. Wherein, every output terminal of the source drive is electrically connected to a conventional DAC as shown in FIG. 1. Referring to FIG. 1, a conventional DAC (a DAC with 3-bits resolution is taken as exemplary herein) includes three switch units 101˜103. The switch units 101˜103 are respectively controlled by bits b[3]˜b[1], wherein the switches in each switch unit are allocated in couples (for example, SW17 and SW18; SW13 and SW14) and the coupled switches are electrically connected to a same switch. In addition, the coupled switches are controlled by a bit and the phase-inverted bit of the bit, respectively (for example, the switches SW18 and SW17 are respectively controlled by the bit b[1] and the phase-inverted bit thereof /b[1]. Therefore, the reference voltages V1˜V8 to be input to the conventional DAC are sequentially delivered through the switching operations of the switch units from 101 to 103 under the controls of the digital signals b[3]˜b[1]. In this way, the switch unit 101 selects half of the reference voltages from the reference voltages V1˜V8 for outputting and delivering to the switch unit 102. Afterwards, through the switching operation of the switch unit 102, the received four reference voltages (for example, V1, V3, V5 and V7) are selected into two reference voltages for outputting to the switch unit 101. The switch unit 101 would, through switching, select a reference voltage as the output analog signal Vout1 of the conventional DAC.
According to the above mentioned, a conventional DAC employs multiple switches to implement the switching on the reference voltages. Such a scheme, however, requires a huge number of switches for numerous DACs to be disposed in a source driving circuit, which indicates an excessive cost a TFT LCD needs.
To solve the above-described problem, another conventional DAC 210 was provided. Referring to FIG. 2, the conventional DAC 210 is formed by a conventional DAC 110 and switches SW21 and SW22. The switches SW21 and SW22 are respectively coupled with the output terminal of the conventional DAC 110 to further create two signal output terminals Pout21 and Pout22 controlled by timing switching signals SWCLK21 and SWCLK22. Thus, every two output terminals of a source driver share a same DAC, which is advantageous to downsize the chip area. Wherein, the analog signals are output phase by phase as shown in FIG. 3, which can be achieved by using two non-overlapped timing switching signals SWCLK21 and SWCLK22. When the timing switching signal SWCLK21 turns on the switch SW21, an analog signal VOUT21 is produced and delivered to the signal output terminal POUT21; when the timing switching signal SWCLK22 turns on the switch SW22, an analog signal VOUT22 is produced and delivered to the signal output terminal POUT22.
Although the above-mentioned conventional DAC 210 functions to downsize a chip area, however, it only allows a half of the output terminals of a source driver being able to drive pixels at any time under the ‘phase by phase outputting’ mode. Under the situation, the available charging time each output terminal can provide to the pixels needs to be shortened, and the available charging time is reduced proportionally with the number of the DACs the output terminals share. In comparison with the conventional DAC 110, on each switching path of the conventional DAC 210, an extra switch is required to be disposed (as shown by the arrows 104 and 201 in FIG. 1 and FIG. 2). Thus, to avoid the increase of the equivalent resistor, the conventional DAC 210 is forced to adopt the switches (SW21 and SW22) with a larger layout area in order to maintain the original performance of the source driver.